During the design and development of new integrated circuits (ICs), it is necessary to test the performance of these ICs relative to the required specifications. Exemplary optical fault analysis methods include Laser Scanning Microscopy (LSM), Laser Voltage Imaging (LVI) and Laser Voltage Probing (LVP). Optical methods may take advantage of minute (˜600 ppm) changes in the reflectivity of conduction regions (e.g., source-gate-drain) arising from voltage-induced changes in carrier concentrations. Some functional testing must be performed on completed ICs, i.e., ICs already having many metal interconnect layers on top of the device layer containing the transistors and other active elements to be tested. Optical imaging for testing or imaging purposes is not possible “looking” through the metal interconnects (the “frontside” of the device) which are opaque to all wavelengths of light. In some applications, optical imaging through the backside of the device (“looking” through the silicon substrate) may require using infrared (IR) light due to the silicon bandgap which causes absorption of light with shorter wavelengths. In other applications, the chip may be backside-thinned to enable the use of shorter wavelengths. In still other applications, alternative methods and wavelengths may be employed to obtain optical images.
As the semiconductor industry has progressed to new device nodes every two to three years, and wherein each node represents about a 30% reduction (1/√2 times smaller) in feature sizes, the smallest features on state-of-the-art devices now range to below 20 nm—smaller than the optical resolution achievable with current state-of-the-art optical imaging techniques
Typically, a user would like to test, i.e., observe the electrical performance of, various circuit elements within a “sea” of logic defined in a computer-aided design (CAD) database. Typically, the CAD database will contain multiple layers which define the structures within an IC from the substrate to the top of the metal interconnect layers. Backside optical images do not visualize all of these layers, typically only observing the device layer and a few layers above that within the interconnect stack, wherein the imaging of these “higher” layers may be lower contrast or possibly blurred. Usually no fiducial marks are available to aid the alignment of the CAD data to the device image since fiducials would occupy valuable area on the IC which could be better used for devices (maximizing device packing and minimizing the IC size). Thus, the alignment of the CAD data to the device image must usually be performed using the image itself. However due to basic optics considerations, the image resolution may be poorer than the device geometries to be imaged and tested. This makes accurate alignment (registration) between the CAD data and the device image difficult and imprecise. Coarse CAD data-to-image registration may be performed using global alignment of the CAD data to the microscope stage (which itself is aligned to the device). Fine alignment at the nm-level (i.e., smaller than the device geometries) becomes more difficult, and with increasing failure rates, as device continue to shrink with each new device node.
Thus, there is a need for methods to improve the registration precision between the IC CAD data and the optical images to ensure that functional data may be obtained from the exact circuit features of interest, even when surrounded by large numbers of similar features in the IC. As is well known, the CAD data already comprises sharply-defined edges, typically with X- or Y-orientations, surrounding rectangular shapes which may be displayed in either outline or filled-in polygon form. However, the optical images are quite blurry due to resolution limitations of the backside optical imaging systems. To improve CAD data to image registration, it is reasonable to look to methods of image enhancement as a first step towards improving CAD data to image registration.
A pressing need also exists to observe the propagation of electrical signals within the IC under test. This essentially would involve processing of the CAD device pattern data to extract those patterns which are expected to appear in the optical image of the operational device. The processed CAD data may be further improved to demonstrate dynamic behavior when the device is subjected to a pre-determined ac test signal. An example might be the gate and drain voltages of the two transistors within an inverter, surrounded by other transistors which are static (i.e., not switching). Combined with resolution enhancement, a X-Y overlay of the dynamic device structures from the CAD data to the dynamic features on the device under test (DUT) may be accomplished with much higher accuracy.
Another need is to perform probing measurements on DUTs in a much more timely manner than is possible with current LVP methods in which the beam is stationary on part of a device (e.g., a gate) over a period of minutes required to obtain full voltage waveforms. The reason for such lengthy measurement is that the noise amplitude on the acquired periodic signal is too high and it is necessary to collect for a long time and average over the full collection time. During averaging, the signal stays the same but the averaging process decreases the portion of noise in the total signal. Therefore, it is necessary to wait a long time at the stationary probe location. However, when LVI data is acquired, collection is in the frequency domain and the noise is spread across all frequencies.
To optimize the alignment of the CAD data to the optical images, thus it may be beneficial to reconstruct the images and also to process the CAD data to more closely match these reconstructed images.